1. Field of the Invention
The present invention relates to a constant voltage circuit featuring reduced power consumption and to an analog electronic clock.
2. Background Art
FIG. 3 is a block diagram of an analog electronic clock. The analog electronic clock includes a semiconductor device 1, a crystal 2, a battery 3, and a motor 4. The semiconductor device 1 includes an oscillation circuit 11, to which the crystal 2 is connected, a frequency division circuit 12, a constant voltage circuit 10, which outputs a constant voltage Vreg for driving the oscillation circuit 11 and the frequency division circuit 12, and an output circuit 13 which drives the motor 4.
An analog electronic clock is required to minimize the frequency of replacing the battery thereof, so that the semiconductor device 1 is required to reduce current consumption. As a method for reducing the current consumption, the constant voltage circuit 10 that consumes less current has been proposed (refer to Patent Document 1).
FIG. 4 is a block diagram of a conventional constant voltage circuit. The conventional constant voltage circuit 10 includes a reference voltage circuit 101 that generates a reference voltage Vref, a differential amplifier circuit 102, an output transistor 103, a voltage dividing circuit 104, a holding circuit 105 composed of a capacitor, and a switch circuit 106.
The conventional constant voltage circuit 10 has the holding circuit 105 that holds the gate voltage of the output transistor 103, and reduces power consumption by intermittently operating the differential amplifier circuit 102 and the like. The operation of the differential amplifier circuit 102 is interrupted by a signal Φ1 and the switch circuit 106 is turned off. At this time, the gate voltage of the output transistor 103 is held by the holding circuit 105 at a voltage before the switch circuit 106 was turned off. Unless a load current significantly varies, the constant voltage circuit 10 is capable of outputting the constant voltage Vreg.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-298523
However, the conventional constant voltage circuit 10 is incapable of maintaining an output voltage in the case where a load current significantly varies. More specifically, if a battery voltage suddenly falls while the switch circuit 106 is off, then the gate-source voltage of the output transistor 103 decreases, undesirably causing the constant voltage Vreg to vary. Further, if the constant voltage Vreg falls below an oscillation stop voltage VDOS of the oscillation circuit 11, then the oscillation circuit 11 may lose stability and stop oscillation.